Named after Brian Josephson — Nobel 1973 — who predicted the Josephson junction theoretically before it was ever fabricated. QJosephson does the same for your QPU: predict before you build.
Palace is the gold standard for full 3D chip simulation. But not every simulation problem is 3D. Cross-sectional analysis — transmission line geometry, CPW field profiles, inductance per unit length — requires a different solver. QJosephson uses both, automatically selecting the right tool for each task.
Palace operates exclusively in 3D. Cross-sectional problems require either an unnecessarily expensive 3D approximation or a dedicated 2D solver. This is where Elmer complements Palace.
Elmer's 2D cross-sectional results are approximations for a full 3D chip. Final T₁ validation always requires a full Palace 3D run.
Accepts KQCircuits Python designs, GDS II files, or plain-text chip descriptions. Parses the full layer stack, identifies junctions, pads, resonators, airbridges, and ground planes. Reconstructs a clean 3D geometry with correct material assignments for both Palace and Elmer meshing.
QJosephson automatically decomposes the simulation task. Cross-sectional problems are dispatched to Elmer. Full chip eigenmode analysis goes to Palace. Both solvers are configured automatically — mesh density, boundary conditions, convergence targets — tuned for superconducting qubit geometries.
Computes the energy participation ratio for all five critical dielectric interfaces: metal-air top (MA-top), metal-air sidewall (MA-side), metal-air bottom (MA-bottom), substrate-air (SA), and metal-substrate (MS). The output is a complete interface loss budget showing which surface dominates T₁ limitation for this specific geometry.
Applies process-specific loss tangent values (tan δ) to convert EPR participation ratios into a predicted T₁. LossDB stores tan δ values organized by fabrication process — Nb on high-resistivity Si, Nb on sapphire, Al on Si, NbTiN on Si — each calibrated against real chip measurements.
Compares the predicted T₁ against the historical distribution of measured T₁ values from chips simulated with the same process parameters. Generates a verification confidence score and flags predictions that disagree beyond expected variance before the design proceeds to optimisation.
Semiconductor EDA tools have had multi-objective geometry optimisation for decades. QJosephson brings the same intelligence to superconducting QPU design.
The design optimisation engine treats QPU geometry as a high-dimensional parameter space and uses Bayesian Optimisation (BO) to find the geometry that maximises T₁ subject to fabrication constraints. BO is sample-efficient, works well in 10–50 dimensional spaces, and provides uncertainty estimates alongside each recommendation.
After 50–200 evaluations, BO converges on a Pareto-optimal design that the engineer could not have found manually in weeks of iteration.
QJosephson trains a Gaussian Process (GP) surrogate on completed simulation results — enabling 100× faster T₁ estimates. The GP provides uncertainty estimates: regions with high uncertainty are prioritised for true Palace simulations, minimising total compute time.
Maximising T₁ trades against anharmonicity, coupling strength, frequency targeting, and fabrication yield. QJosephson returns the full Pareto front — a set of designs where no objective can be improved without degrading another.
A domain-specific neural network trained on superconducting qubit design data: thousands of simulated and measured transmon, fluxonium, and cat qubit geometries with their corresponding eigenfrequencies, anharmonicities, and T₁ values.
QJosephson integrates process design rules — minimum feature size, junction aspect ratio limits, proximity rules, etching bias — as hard constraints. Every candidate reaching Palace validation is tapeout-ready without manual DRC review.
For each geometric parameter, how much does T₁ change per unit variation? The sensitivity map tells the engineer which dimensions matter most for coherence — and therefore which fabrication tolerances to tighten.
| Feature | QJosephson | ANSYS HFSS | COMSOL RF | Palace standalone | pyEPR |
|---|---|---|---|---|---|
| Purpose-built for superconducting QPU | Yes | No | No | Partial | Yes |
| KQCircuits geometry import | Yes | Manual | No | No | No |
| 3D FEM solver (Palace) | Yes | Yes | Yes | Yes | No |
| 2D cross-section solver (Elmer) | Yes | No | Manual | No | No |
| Automatic solver routing (2D/3D) | Yes | No | No | No | No |
| Auto EPR extraction (all 5 interfaces) | Yes | No | No | Partial | Partial |
| T₁ prediction from geometry | Yes | No | No | No | No |
| Fabrication-calibrated loss database | Yes | No | No | No | No |
| Bayesian geometry optimisation | Yes | No | No | No | No |
| GP surrogate model (100× faster sweeps) | Yes | No | No | No | No |
| Trained QPU foundation model | Yes | No | No | No | No |
| Verification confidence score | Yes | No | No | No | No |
| T₁ sensitivity map | Yes | Manual | Manual | No | No |
| Natural language geometry input | Yes | No | No | No | No |
| Requires FEM expertise to operate | No | Yes | Yes | Yes | Partial |
| Licence cost | €15–40K/yr | €20–50K/yr | €10–30K/yr | Free | Free |
| Improves with chip measurement data | Yes | No | No | No | No |
Josephson predicted the quantum tunnelling of Cooper pairs through a thin insulating barrier — theoretically, before a single junction had been fabricated. The effect was verified experimentally two years later and now underpins every superconducting qubit in existence.
QJosephson is in active development. If you are a quantum hardware company, a university lab designing superconducting circuits, or an investor interested in quantum EDA, we want to hear from you.